1. Field of the Invention
The present invention relates generally to improving the performance of integrated circuit components and, more particularly, to reducing variation in dynamic random access memory (DRAM) cell retention time.
2. Background of the Related Art
This section is intended to introduce the reader to various aspects of art, which may be related to various aspects of the present invention, which are described and/or claimed below. This discussion is believed to be helpful in providing the reader with background information to facilitate a better understanding of the various aspects of the present invention. Accordingly, it should be understood that these statements are to be read in this light, and not as admissions of prior art.
Integrated circuits are used in a wide variety of applications throughout the world. Such applications include personal computers, control systems, telephone networks, and a host of other consumer products. Memory devices, such as dynamic random access memory (DRAM) integrated circuits, may be used for storing information in electronic devices. As the speed of microprocessor-based circuits increases, demand increases for high speed memory devices, which require increasingly fast and accurate timing and control.
Memory manufacturers, such as the assignee of the present invention, provide an array of innovative fast memory chips for various applications. DRAM, which is widely used, is relatively inexpensive to manufacture compared to other types of memory (for example, static random access memory). One disadvantage of DRAM, however, is that the data stored in DRAM must constantly be re-written or “refreshed” or the data will be lost. For this reason, DRAM is considered to be “volatile.” Other types of memory that maintain data permanently are referred to as “non-volatile” memory. The lower cost and higher density of DRAM make it an excellent choice for applications that require relatively large amounts of memory, such as computer systems.
Each DRAM is comprised of a very large number of individual memory cells. There may be millions of these memory cells in a single DRAM integrated circuit device. Each individual memory cell holds one bit of information, which may be a logical low (“0”) or a logical high (“1”). Bit is short for “binary digit” and is the basic data unit in personal computers and other microprocessor-based systems. The memory cells each comprise a transistor and a capacitor. The memory cells are arranged in rows and columns, with the rows are word lines (RB) connected to a bitline, and the columns are bitlines (RB) connected to a wordline. The capacitor is either charged (a logical “1” in most systems) or discharged (a logical “0” in most systems). A DRAM cell may also be referred to as a “DRAM bit” because each cell holds one bit.
To store a “1” in a memory cell, the corresponding capacitor is depleted of electrons (or positively charged). To store a “0”, the capacitor is not charged (RB). One problem is that capacitors tend to leak over time. Depending on its physical characteristics, a full capacitor can become empty (or discharged) in a relatively short time (about 64 milliseconds). Therefore, for dynamic memory to work, either the microprocessor (central processing unit or CPU) or a memory controller must repeatedly recharge or refresh all of the capacitors holding a charge (i.e. “1”) before the capacitors discharge. To do this, the memory controller or CPU may read the data stored in each memory cell and then write the data that it read back into the corresponding memory cell. This refresh operation is where DRAM gets its name. DRAM must be dynamically refreshed or it loses the data that it is holding.
Refresh circuits may operate on entire rows of memory cells. This eliminates the need of having to refresh each memory cell individually. During a refresh cycle, the refresh circuit may read out and write back an entire row of memory in a single operation. The transistor in each DRAM cell acts as a switch that lets the refresh circuitry on the DRAM chip read the capacitor or change the capacitor's state.
Inherent defects in the DRAM cell transistors are believed to cause variation in the length of time that the capacitor and thus the overall DRAM cell retains a charge. Significant research and development has been devoted to reducing variability in DRAM charge retention time caused by transistor defects.
The retention time, or length of time that a DRAM cell may hold a charge before needing to be refreshed, is typically measured in milliseconds and is sometimes called refresh time. In a typical DRAM cell, retention time tends to decrease as ambient temperature increases. Ideally, however, retention time of a DRAM cell should remain constant at a given temperature. Unfortunately, external factors such as time are believed to affect retention time in some DRAM cells. For example, some DRAM cells are believed to experience changes in retention time as time passes (even at a constant temperature). This variability in retention time is undesirable.
Predictability and consistency of retention time is important in being able to accurately quantify the performance of DRAM devices. If the retention time for cells of a DRAM device change over time or temperature, it may be hard to specify a guaranteed minimum refresh rate for the device. This problem is complicated by the fact that the retention times for some cells in a DRAM device may vary while the retention time for other memory cells remains more or less constant. Unless the DRAM device is refreshed at a rate that is shorter than the minimum retention time of any of the memory cells under any conditions, data stored in the DRAM device may potentially be lost. This problem is accentuated by the fact that variations in retention time for DRAM cells are not predictable. Because DRAM devices may have millions of individual cells, identifying the shortest retention time of any of the cell in the entire device, or even the conditions that cause the lowest retention time to occur, may be impossible to determine. Picking a needlessly short retention time to account for possible variations in individual memory cells is not an effective option because an unduly short retention time means that the circuitry that performs the refresh operation will be operating more frequently and consuming more power than necessary.
One theory about the cause of variable retention time is that imperfections in the transistor semi-conductor material contribute to the variation. More specifically, mobile defects in the transistor p-n junction may cause the variation. These junctions are basic building blocks in many integrated circuit devices, so the same factors that cause variable retention time may also be responsible for creating problems in the operation of other semiconductor devices as well. Whatever the cause, variation in retention time is undesirable, and a method of reducing the incidence of variable retention time in DRAM cells is desirable.